////////////////////////////////////////////////////////////////////////////////
/// @file    sdio.c
/// @author  AE TEAM
/// @brief   THIS FILE PROVIDES ALL THE SYSTEM FUNCTIONS.
////////////////////////////////////////////////////////////////////////////////
/// @attention
///
/// THE EXISTING FIRMWARE IS ONLY FOR REFERENCE, WHICH IS DESIGNED TO PROVIDE
/// CUSTOMERS WITH CODING INFORMATION ABOUT THEIR PRODUCTS SO THEY CAN SAVE
/// TIME. THEREFORE, MINDMOTION SHALL NOT BE LIABLE FOR ANY DIRECT, INDIRECT OR
/// CONSEQUENTIAL DAMAGES ABOUT ANY CLAIMS ARISING OUT OF THE CONTENT OF SUCH
/// HARDWARE AND/OR THE USE OF THE CODING INFORMATION CONTAINED HEREIN IN
/// CONNECTION WITH PRODUCTS MADE BY CUSTOMERS.
///
/// <H2><CENTER>&COPY; COPYRIGHT MINDMOTION </CENTER></H2>
////////////////////////////////////////////////////////////////////////////////
// Define to prevent recursive inclusion
#define _SDIO_C_

// Files includes

#include "SDIO.h"
#include "uart.h"
#include "sdio_sdcard.h"
#include "delay.h"
////////////////////////////////////////////////////////////////////////////////
/// @addtogroup MM32_Example_Layer
/// @{

////////////////////////////////////////////////////////////////////////////////
/// @addtogroup SDIO
/// @{

////////////////////////////////////////////////////////////////////////////////
/// @addtogroup SDIO_Exported_Constants
/// @{

extern u32 SystemCoreClock;
////////////////////////////////////////////////////////////////////////////////
/// @brief  SDIO GPIO remap config.
/// @param  None.
/// @retval  0.
////////////////////////////////////////////////////////////////////////////////
void SDIO1_GPIOAF_Init(void)
{
    GPIOC->CRH &= 0x0;
    GPIOC->AFRH &= 0x0;

    GPIOC->CRH &= 0xFFFFFFF0;   //GPIOC_Pin_8 clear
    GPIOC->CRH |= 0x00000008;   //GPIOC_Pin_8 CNF
    GPIOC->CRH |= 0x1 << 1;    //GPIOC_Pin_8 SDIO_data[0] MODE:AF_PP
    GPIOC->AFRH |= 0x0000000C;

    GPIOC->CRH &= 0xFFFFFF0F;   //GPIOC_Pin_9 clear
    GPIOC->CRH |= 0x00000080;   //GPIOC_Pin_9 CNF
    GPIOC->CRH |= 0x1 << 5;    //GPIOC_Pin_9 SDIO_data[1] MODE:AF_PP
    GPIOC->AFRH |= 0x000000C0;

    GPIOC->CRH &= 0xFFFFF0FF;   //GPIOC_Pin_10 clear
    GPIOC->CRH |= 0x00000800;   //GPIOC_Pin_10 CNF
    GPIOC->CRH |= 0x1 << 9;     //GPIOC_Pin_10 SDIO_data[2] MODE:AF_PP
    GPIOC->AFRH |= 0xC00;

    GPIOC->CRH &= 0xFFFF0FFF;   //GPIOC_Pin_11 clear
    GPIOC->CRH |= 0x00008000;   //GPIOC_Pin_11 CNF
    GPIOC->CRH |= 0x1 << 13;    //GPIOC_Pin_11 SDIO_data[3] MODE:AF_PP
    GPIOC->AFRH |= 0xC000;

    GPIOC->CRH &= 0xFFF0FFFF;   //GPIOC_Pin_12 clear
    GPIOC->CRH |= 0x00080000;   //GPIOC_Pin_12 CNF
    GPIOC->CRH |= 0x1 << 17;    //GPIOC_Pin_12 SDIO_ck MODE:AF_PP
    GPIOC->AFRH |= 0xC0000;

    GPIOD->CRL &= 0xFFFFF0FF;   //GPIOD_Pin_2 clear
    GPIOD->CRL |= 0x00000800;   //GPIOD_Pin_2 CNF
    GPIOD->CRL |= 0x1 << 9;    //GPIOD_Pin_2 SDIO_CMD MODE:AF_PP
    GPIOD->AFRL &= 0xFFFFF0FF;
    GPIOD->AFRL |= 0xC00;
}
////////////////////////////////////////////////////////////////////////////////
/// @brief  SDIO initialize.
/// @param  None.
/// @retval  0.
////////////////////////////////////////////////////////////////////////////////
void SDIO_ConfigInit(void)
{
//    const u32 targetFreq=24000000;
//    u32 clk;
//    RCC_ClocksTypeDef bclk;
    SDIO1_GPIOAF_Init();
//    clk = (SystemCoreClock / 1600000 - 1);
//    RCC_GetClocksFreq(&bclk);
//    clk = (bclk.HCLK_Frequency / 24000000 - 1);
    SDIO_ClockSet(0x2F);
    //SDIO->MMC_CARDSEL = 0xdf;

    SDIO_InitTypeDef SDIO_InitStruct;
    SDIO_InitStruct.SDIO_OPMSel = SDIO_MMC_CTRL_OPMSel;
    SDIO_InitStruct.SDIO_SelPTSM = SDIO_MMC_CTRL_SelSM;
    SDIO_InitStruct.SDIO_DATWT = SDIO_MMC_CTRL_DATWT;
    SDIO_Init(&SDIO_InitStruct);
    SDIO_ITConfig(SDIO_MMC_INT_MASK_CMDDINT, ENABLE);
    SDIO_CRCConfig(SDIO_MMC_CRCCTL_CMD_CRCEN | SDIO_MMC_CRCCTL_DAT_CRCEN, ENABLE);
}

/// @}

/// @}

/// @}

